SN74LV27A Datasheet | Texas Instruments

Features - Operation of 2-V to 5.5-V VCC - Max tpd of 7 ns at 5 V - Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C - Ioff Supports Partial-Power-Down Mode Operation - Latch-Up Performance Exceeds 100 m A Per JESD 78, Class II 2 Description These triple 3-input positive-NOR gates are designed for 2-V to 5.5-V VCC operation. The SN74LV27A devices perform the Boolean function Y = A + B + C in positive logic. These devices are fully specified for partial-powerdown applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. Package Information PART NUMBER PACKAGE1 PACKAGE SIZE2 DGV (TVSOP, 14) 3.60 mm x 6.4 mm D (SOIC, 14) 8.65 mm x 6 mm NS (SO, 14) 10.20 mm x 7.8 mm DB (SSOP, 14) 6.20 mm x 7.8 mm PW (TSSOP, 14) 5.00 mm x 6.4 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. x A x B x Y x C Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. SCES341F - SEPTEMBER 2000 - REVISED JULY 2023 .ti. Table of Contents 1 Features 1 2 Description 1 3 Revision History 2 4 Pin Configuration and Functions 3 5 Specifications 4 5.1 Absolute Maximum Ratings 4 5.2 ESD...